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micro p ower quad - channel digital isolat ors data sheet adum1440 / adum1 441/ adum1442 / adum1445 / adum1446 / adum1447 features ultra l ow power operation 3.3 v operation ( t ypical ) 5.6 a per channel quiescent current, refresh enabled 0.3 a per channel quiescent current, refresh disabled 148 a/mbps per channel typical dynamic current 2.5 v operation ( t ypical) 3 . 1 a per c hannel quiescent current, refresh enabled 0.1 a per channel quiescent current, refresh disabled 117 a/mbps per channel typical dynamic current small, 16 - lead qsop bidirectional communication up to 2 mbps data rate ( nrz ) high temperature operation: 125c high common - mode transient immunity: >25 kv/ s safety and regulatory approvals ul 1577 component r ecognition program (pending) 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a ( pending) vde c ertificate of c onformity (pending) din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 v iorm = 560 v peak applications general - purpose, low power multichannel isolation 1 mhz , low power peripheral interface ( spi ) 4 ma to 20 ma l oop process control s g eneral description the adum1440 / adum1441 / adum1442 / adum1445 / adu m1446 / adum1447 1 are micropower , 4 - channel digital isolators based on the analog devices, inc., i coupler? technology. combining high speed , complementary metal oxide semiconductor (cmos) and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to the alternatives, such as optocoupler devices. as shown in figure 2 , in standard operating mode, when en x = 0 (internal refresh enabled) , the current per channel is less than 10 a. when en x = 1 (internal refresh disabled), the current per channel drops to less than 1 a. functional block dia gram encode decode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic /v oc v id /v od en 1 gnd 1 v dd2 gnd 2 v oa v ob v oc /v ic v od /v id en 2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 adum144x qsop 1 1845-002 figure 1. the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 family of quad 2.5 kv digital isolation devices are packaged in a small 16 - lead qsop, freeing almost 70% of board space compared to isolator s packages in wide body soic packages. the devices withstand high isolation voltages and meet regulatory requirements, such as ul and csa standards (pending). in addition to the space savings, the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 operate with supplies as low as 2.25 v. despite the low power consumption, all models of the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 prov ide low, pulse width distortion at <8 ns. in additio n, every model has an input glitch filter to protect against extraneous noise disturbances. 0.1 1 10 100 1000 0.1 1 10 100 1000 10000 current per channe l ( a) d at a r a te (mbps) en x = 1 en x = 0 1 1845-001 figure 2 . typical total supply current per channel ( v ddx = 3.3 v ) 1 protected by u.s. patents 5,952,849, 6,873,065, 7,075,329, 6,262,60 0. other patents pending. rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may res ult from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical s upport www.analog.com
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 3.3 v operation ............................ 3 electrical characteristics 2.5 v operation ............................ 5 electrical characteristics v dd1 = 3.3 v, v dd2 = 2.5 v operation ....................................................................................... 7 electrical characteristics v dd1 = 2.5 v, v dd2 = 3.3 v operation ....................................................................................... 8 package characteristics ............................................................... 9 regulatory information ............................................................... 9 insulation and safety - rel ated specifications ............................ 9 din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 insulation characteristics ............................................................................ 10 recommended operating conditions .................................... 10 absolute maximum ratings ......................................................... 11 esd caution ................................................................................ 11 pin configuration s and function descriptions ......................... 12 typical performance characteristics ........................................... 15 applications information .............................................................. 18 printed circuit board (pcb) layout ....................................... 18 propagation delay - related parameters ................................... 18 dc correctness ............................................................................ 18 magnetic field immunity ............................................................. 19 power consumption .................................................................. 20 insulation lif etime ..................................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 1 0 /13 revision 0: initial v ersion rev. 0 | page 2 of 24
data sheet adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 specifications electrical character istics 3.3 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.3 v. minimum/maximum specifications apply over the entire recommended operatin g range of 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v, a n d ? 40c t a + 125c , unless otherwise noted. switching specifications are tested with c l = 15 pf, and cmos signal levels, unless otherwise noted. table 1 . parameter symbol min typ max unit test conditions/comments switchin g specifications data rate 2 mbps within pulse - width distortion ( pwd ) limit propagation delay t phl , t plh 80 1 8 0 ns 50% input to 50% output change vs. temperature 200 ps/c minimum pulse width pw 500 ns within pwd limit pulse - width dist ortion pwd 8 ns |t plh ? t phl | propagation delay skew 1 t psk 10 ns channel matching codirectional t pskcd 10 ns opposing direction t pskod 15 ns 1 t psk is the magnitude of the worst - case difference in t phl and t plh that is measured between units at the same operating temper ature, supply voltages, and output load within the recommended operating conditions. table 2 . parameter symbol min typ max unit test conditions/comments supply current 2 mbps, no load adum1440 / adum1445 i dd1 732 1000 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 492 750 a en x = 0 v, v ih = v dd , v il = 0 v adum1441 / adum1 446 i dd1 672 900 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 552 900 a en x = 0 v, v ih = v dd , v il = 0 v adum1442 / adum1447 i dd1 612 900 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 612 900 a en x = 0 v, v ih = v dd , v il = 0 v rev. 0 | page 3 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet table 3 . for all models parameter symbol min typ max unit test cond itions/comments dc specifications input threshold logic high v ih 0.7 v ddx 1 v logic low v il 0.3 v ddx 1 v output voltages logic high v oh v ddx 1 ? 0.1 3.0 v i o ut x = ?20 a, v ix = v ixh v ddx 1 ? 0.4 2.8 v i o ut x = ?4 ma, v ix = v ixh logic low v ol 0.0 0.1 v i o ut x = 20 a, v ix = v ixl 0.2 0.4 v i o ut x = 4 ma, v ix = v ixl input current per channel i i ?1 +0.01 +1 a 0 v v ix v ddx 1 input switching thresholds positive threshold voltage v t+ 1.8 v negative going threshold v t ? 1.2 v input hysteresis v t 0.6 v under v oltage lockout, v dd1 or v dd2 uvlo 1.5 v supply current per channel quiescent current input supply i ddi (q) 4.8 10 a en x l ow output supply i ddo (q) 0.8 3.3 a en x low input ( refresh o ff ) i ddi (q) 0.12 a en x h igh output ( refresh o ff ) i ddo (q) 0.13 a en x h igh dynamic supply current input i ddi (d) 88 a/mbps output i ddo (d) 60 a/mbps ac specifications output rise time /fall time t r /t f 2 ns 10% to 90% common - mode transient immunity 2 |cm| 25 40 kv/s v ix = v ddx 1 , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 14 kbps 1 v ddx = v dd1 or v dd2 . 2 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o ut > 0.8 v dd x . the common - mode voltage slew rates appl y to both rising and falling common - mode voltage edges. rev. 0 | page 4 of 24
data sheet adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 electrical character istics 2.5 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 2.5 v. minimum/maxim um specifications apply over the entire recommended operatin g range of 2.25 v v dd1 2.75 v, 2.25 v v dd2 2. 75 v, and ?40c t a + 125c , unless otherwise noted. switching specifications are tested with c l = 15 pf, and cmos signal levels, unless otherwise noted. table 4 . parameter symbol min typ max unit test conditions/comments switching specifications data rate 2 mbps within pwd limit propagation delay t phl , t plh 112 180 ns 50% input to 50% output change vs. temperature 280 ps/c pulse - width distortion pwd 12 ns |t plh ? t ph l | minimum pulse width pw 500 ns within pwd limit propagation delay skew 1 t psk 10 ns channel matching codirectional t pskcd 10 ns opposing direction t pskod 30 ns 1 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. table 5 . parameter symbol min typ max unit test conditions/comments supply current 2 mbps, no load adum1440 / adum1 445 i dd1 623 800 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 337 500 a en x = 0 v, v ih = v dd , v il = 0 v adum1441 / adum1446 i dd1 552 750 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 409 750 a en x = 0 v, v ih = v dd , v il = 0 v adum1442 / adum1447 i dd1 480 750 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 480 750 a en x = 0 v, v ih = v dd , v il = 0 v rev. 0 | page 5 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet table 6 . for all model s parameter symbol min typ max unit test conditions/comments dc specifications input threshold logic high v ih 0.7 v ddx 1 v logic low v il 0.3 v ddx 1 v output voltages logic high v oh v ddx 1 ? 0.1 2.5 v i ox = ?20 a, v ix = v ixh v ddx 1 ? 0.4 2.35 v i ox = ?4 ma, v ix = v ixh logic low v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.1 0.4 v i ox = 4 ma, v ix = v ixl input current per cha nnel i i ?1 +0.01 +1 a 0 v v ix v ddx 1 input switching thresholds positive threshold voltage v t+ 1.5 v negative going threshold v t? 1.0 v input hysteresis v t 0.5 v under v oltage lockout, v dd1 or v dd 2 uvlo 1. 5 v supply current per channel quiescent current input supply i ddi (q) 2.6 3.3 a en x low output supply i ddo (q) 0.5 1.8 a en x low input (refresh off ) i ddi (q) 0.05 a en x high output (refresh off ) i ddo (q) 0.05 a e n x high dynamic supply current input i ddi (d) 76 a/mbps output i ddo (d) 41 a/mbps ac specifications output rise time /fall time t r /t f 2 ns 10% to 90% common - mode transient immunity 2 |cm| 25 40 kv/s v ix = v ddx 1 , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 14 kbps 1 v ddx = v dd1 or v dd2 . 2 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o ut > 0.8 v dd x . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. rev. 0 | page 6 of 24
data sheet adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 electrical character istics v dd1 = 3.3 v, v dd2 = 2.5 v operation all typical specifications are at t a = 25c, v dd1 = 3.3 v, and.v dd2 = 2.5 v. minimum/maximum specifications apply over the entire recommended operatin g range of 3.0 v v dd1 3.6 v, 2.25 v v dd2 2. 75 v, and ?40c t a + 125c , unless otherwise noted. switching specifications are tested with c l = 15 pf, and cmos signal levels, unless otherwise noted. for dc specifications and ac specifications, see table 3 for side 1 and see table 6 for side 2. table 7 . parameter symbol min typ max unit test conditions/comments switching specifications data rate 2 mbps within pwd limit propagatio n delay side 1 to side 2 t phl , t plh 84 1 8 0 ns 50% input to 50% output side 2 to side 1 t phl , t plh 120 180 ns 50% input to 50% output change vs. temperature 280 ps/c pulse - width distortion pwd 12 ns |t plh ? t phl | pulse width pw 500 ns within pwd limit propagation delay skew 1 t psk 10 ns channel matching codirectional t pskcd 10 ns opposing direction t pskod 60 ns 1 t psk is the ma gnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. table 8 . parameter symbol min typ max unit tes t conditions/comments supply current 2 mbps, no load adum1440 / adum1445 i dd1 732 1000 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 337 750 a en x = 0 v, v ih = v dd , v il = 0 v adum1441 / adum1446 i dd1 672 900 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 409 750 a en x = 0 v, v ih = v dd , v il = 0 v adum1442 / adum1447 i dd1 612 900 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 480 750 a en x = 0 v, v ih = v dd , v il = 0 v rev. 0 | page 7 of 24
adum1440/adum1441/adum1442/ adum1445/adum1446/adum1447 data sheet electrical character istics v dd1 = 2.5 v, v dd2 = 3. 3 v operation all typical specifications are at t a = 25c, v dd1 = 2.5, and v dd2 = 3.3 v. minimum/maximum specifications apply over the entire recommended operatin g range of 2.25 v v dd1 2.75 v, 3.0 v v dd2 3.6 v, and ?40c t a + 125c , unless other wise noted. switching specifications are tested with c l = 15 pf, and cmos signal levels, unless otherwise noted. for dc specifications and ac specifications, see table 6 for side 1 and see table 3 for sid e 2. table 9 . parameter symbol min typ max unit test conditions/comments switching specifications data rate 2 mbps within pwd limit propagation delay side 1 to side 2 t phl, t plh 120 18 0 ns 50% input to 50% outpu t side 2 to side 1 t phl, t plh 84 1 8 0 ns 50% input to 50% output change vs. temperature 200 ps/c pulse - width distortion pwd 12 ns |t plh ? t phl | pulse width pw 500 ns within pwd limit propagation delay skew 1 t psk 10 ns channel matching codirectional t pskcd 10 ns opposing direction t pskod 60 ns 1 t psk is the magnitude of the worst - case difference in t ph l or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. table 10. parameter symbol min typ max unit test conditions/comments supply current 2 mbps, no load adum1440 / adum1445 i dd1 623 1000 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 492 750 a en x = 0 v, v ih = v dd , v il = 0 v adum1441 / adum1446 i dd1 552 750 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 552 900 a en x = 0 v, v ih = v dd , v il = 0 v adum1442 / adum1447 i dd1 480 750 a en x = 0 v, v ih = v dd , v il = 0 v i dd2 612 900 a en x = 0 v, v ih = v dd , v il = 0 v rev. 0 | page 8 of 24
data sheet adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 package characterist ics table 11. parameter symbol min typ max unit test conditions /comments resistance (input - to - output) 1 r i- o 10 13 ? capacitance (input -to - output) 1 c i- o 2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction - to - ambient thermal resistance ja 76 c/w thermocouple located at center of package underside 1 the device is considered a 2 - terminal device: pin 1 through pin 8 are shorted together, and pin 9 th rough pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regu latory information the adum1440 / adum1441 / adum1442 / adum1445 / adum 1446 / adum1447 are pending approv al by the organizations listed in table 12 . see ta ble 17 and the insulation lifetime section for the recommended maximum working voltages for specific cross - isolation waveforms and insulation levels. table 12. ul (pending) csa (pending) v de ( p ending) recognized under ul 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10):2006- 12 2 single p rotection, 2500 v rms isolation voltage basic insulation per csa 60950 -1 - 03 and iec 60950 - 1, 400 v rms (566 v peak ) maximum working voltage reinforced insulation, 565 v peak file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 is proof tested by applying an insulation test voltage of 3000 v rms for 1 sec (current leakage detection limit = 5 a). 2 in accordance with din v vde v 0884 - 10 , each adum1440/ adum1441 / adum1442 / a dum1445 / adum1446 / adum1447 is proof tested by applying an insulation test vo ltage 1050 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk (*) marked on the component designates din v vde v 0884 - 10 approval. insulation and safet y - related specificatio ns table 13. paramete r symbol value unit test conditions /comments rated dielectric insulation voltage 2500 v rms 1 - minute duration minimum external tracking and air gap (creepage and clearance ) l(i02) 3.1 mm min measured from input terminals to output terminals, shortest distance path along body minimum clearance in the plane of the printed circuit board (pcb clearance) l(i01) 3.8 mm min measured from input terminals to output terminals, shortest distance through air, line of sight, in the pcb mounting plane minimum in ternal gap (internal clearance) 0.017 mm min insulation distance through insulation tracking resistance (comparative tracking index ) cti >400 v din iec 112/vde 0303 part 1 isolation group ii material group (din vde 0110, 1/89, table 1) rev. 0 | page 9 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 insulation character istics these isolators are suitable for reinforced electrical isolation within the safety limit data only. maintenance of the safety data is ensured by protective circuits. the asterisk (*) marked on packages denotes din v vde v 0884 - 10 approval. table 14. description test conditions /comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rat ed mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input - to - output test volta ge, method b1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd(m) 1050 v peak input - to - output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 840 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 672 v peak highest allowable overvoltage v iotm 3500 v peak surge isol ation voltage v peak = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 4000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 3 ) case temperature t s 150 c total power dissipation at 25 c i s1 1.64 w insulation resistance at t s v io = 500 v r s >10 9 ? 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 50 100 150 200 safe limiting power (w) ambient temper a ture ( c) 1 1845-003 figure 3 . thermal derating curve, dependence of safety - limiting values with case temperature per din v vde v 0884 - 10 recommended operatin g conditions table 15. parameter symbol value operating temp erature t a ?40c to +125c supply voltages 1 v dd1 , v dd2 2.25 v to 3.6 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground s . see the dc correctness section for infor mation on immunity to external magnetic fields. rev. 0 | page 10 of 24
data sheet adum1440/adum1441/adum144 2/adum1445/adum1446/adum1447 absolute maximum rat ings t a = 25c, unless otherwise noted. table 16. parameter rating supply voltages (v dd1 , v dd2 ) ?0.5 v to + 3.6 v input voltages (v ia , v ib ) ?0.5 v to v ddi + 0.5 v output voltages (v oa , v ob ) ?0.5 v to v dd2 + 0.5 v average output current per pin 1 side 1 (i o1 ) ?10 ma to +10 ma side 2 (i o2 ) ?10 ma to +10 ma common - mode transients 2 ?100 kv/ s to +100 kv/ s storage temperature (t st ) range ?65c to +150c a mbient operating temperature (t a ) range ?40c to +125c 1 see figure 3 for maximum safety power values for various temperatures. 2 refers to common - mode transients across the insulation barrier. common - mode transi ents exceeding the absolute maximum ratings can cause latch - up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at the se or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 17 . maximum c ontinuous working voltage 1 parameter value constraint ac voltage 60 hz bipolar waveform 565 v peak 50- year minimum lifetime 60 hz unipolar waveform basic insulation 975 v peak 50 - year minimum lifetime dc voltage basic insulation 975 v peak 50- year minimum lifetime 1 refers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. esd caution table 18 . truth table (positive logic) for all models v i x input 1 , 2 v ddi state 3 v ddo state 4 en x input 1 v o x output 1 description h powered powered l h normal operation; data is high and refresh is enabled . l powered powered l l normal operation; data is low and refresh is enabled . h powered powered h h output is high, and refresh is disabled . l powered powered h l 5 output is low, and refresh is disabled . l unpowered powere d l default input unpowered. outputs are in the default state, high for adum1440 , adum1441 , and adum1442 , and l ow adum1445 , adum1446 , and adum1447 . outputs return to input state within 150 s of v ddi power restoration. see the p in function descriptions ( table 19 through table 21) for more details. l unpowered powered h hold input unpowered. outputs are the last state before input power is shut down. x powered unpowered x z output unpowered. output pins are in high impedance state. outputs return to input state within 34 s of v ddo power restoration. see the pin function descriptions ( table 19 through table 21) for more details. 1 h = high, l = low, x = dont care, and z = high impedance. 2 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d). 3 v ddi refers to the power supply on the input side of a given channel (a, b, c, or d). 4 v ddo refers to the power supply on the output side of a given channel (a, b, c, or d). 5 low input must follow a fa lling edge; otherwise, it can be in the default low state. rev. 0 | page 11 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet pin configuration s and function descrip tions v dd1 1 gnd 1 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 2 15 v oa 14 v ob 13 v ic 5 v oc 12 v id 6 v od 11 en 1 7 en 2 10 gnd 1 1 8 gnd 2 2 9 adum1440/ adum1445 top view (not to scale) 1 pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. 2 pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 1 1845-004 figure 4. adum1440 / adum1445 pin configuration table 19. adum1440 / adum1445 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1 (2.25 v to 3.6 v). connect a ceramic bypass capacitor in the 0.01 f to 0.1 f ra nge between v dd1 (pin 1) and gnd 1 (pin 2). 2 , 8 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7 en 1 refresh/watchdog enable 1. connecting pin 7 to gnd 1 enables input/output refresh and watchdog functionality for s ide 1, supporting standard i coupler operation. tying pin 7 to v dd1 disables refresh and watchdog functionality for l owest power operation, see the applications information section for a detailed description of this mode. en 1 and en 2 must be set to the same logic state . 9 , 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 1 5 are internally connected, and connecting both to gnd 2 is recommended. 10 en 2 refresh/watchdog enable 2. connecting pin 10 to gnd 2 enables input/output refresh and watchdog functionality for s ide 2, supporting standard i coupler operation. tying pin 10 to v dd2 disables refresh and watchdog functionality for lowest power operation, see the applications information section for a detailed description of this mode. en 1 and en 2 must be set to the same logic state. 11 v od logic output d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 2 (2.25 v to 3.6 v). connect a ceramic bypass capacitor in the 0.01 f to 0.1 f range between v dd2 (pin 16) and gnd 2 (pin 15). rev. 0 | page 12 of 24
data sheet adum1440/adum1441/adum144 2/adum1445/adum1446/adum1447 v dd1 1 gnd 1 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 2 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 en 1 7 en 2 10 gnd 1 1 8 gnd 2 2 9 adum1441/ adum1446 top view (not to scale) 1 pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. 2 pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 1 1845-005 figure 5. adum1441 / adum1446 pin config uration table 20. adum1441 / adum1446 pin function d escriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1 (2.25 v to 3.6 v). connect a ceramic bypass capacitor in the 0.01 f to 0.1 f range between v dd1 (pin 1) and gnd 1 (pin 2). 2 , 8 gnd 1 ground 1. ground reference for isolat or side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 en 1 refresh/watchdog enable 1. connecting pin 7 to gnd 1 enables inp ut/output refresh and watchdog functionality for s ide 1, supporting standard i coupler operation. tying pin 7 to v dd1 disables refresh and watchdog functionality for lowest power operation, see the applications information section for a detailed description of this mode. en 1 and en 2 must be set to the same logic state . 9 , 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 en 2 refresh/wat chdog enable 2. connecting pin 10 to gnd 2 enables input/output refresh and watchdog functionality for s ide 2, supporting standard i coupler operation. tying pin 10 to v dd2 disables refresh and watchdog functionality for lowest power operation, see the applications information section for a detailed description of this mode. en 1 and en 2 must be set to the same logic state. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply v oltage for isolator side 2 (2.25 v to 3.6 v). connect a ceramic bypass capacitor in the 0.01 f to 0.1 f range between v dd2 (pin 16 ) and gnd 2 (pin 15). rev. 0 | page 13 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet v dd1 1 gnd 1 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 2 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 en 1 7 en 2 10 gnd 1 1 8 gnd 2 2 9 adum1442/ adum1447 top view (not to scale) 1 pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. 2 pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 1 1845-006 figure 6. adum1442 / adum1447 pin configuration table 21. adum1442 / adum1447 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1 (2.25 v to 3.6 v). c onnect a ceramic bypass capacitor in the 0.01 f to 0.1 f range between v dd1 (pin 1) and gnd 1 (pin 2). 2 , 8 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 en 1 refresh/watchdog enable 1. connecting pin 7 to gnd 1 enables input/output refresh and watchdog functionality for s ide 1, supporting standard i coupler operation. tying pin 7 to v dd1 disables refresh and watchdog functionality for lowest power operation, see the applications information section for detailed description of this mode. en 1 and en 2 must be set to the same logic state . 9 , 15 gnd 2 gro und 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 en 2 refresh/watchdog enable 2. connecting pin 10 to gnd 2 enables input/output refresh and watchdog functionality for sid e 2, supporting standard i coupler operation. tying pin 10 to v dd2 disables refresh and watchdog functionality for lowest power operation, see the applications information section for a detailed description of this mode. en 1 and en 2 must be set to the same logic state. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 2 (2.25 v to 3.6 v). connect a ceramic bypass capacitor in the 0.01 f to 0.1 f range between v dd2 (pin 16) and gnd 2 (pin 15). rev. 0 | page 14 of 24
data sheet adum1440/adum1441/adum144 2/adum1445/adum1446/adum1447 typical performance characteristics 0 50 100 150 200 250 300 350 0 500 1000 1500 2000 current consumption per input (a) d at a r a te (kbps) v ddx input current 1 1845-007 0 5 10 15 0 20 40 figure 7 . current consumption per input vs. data rate for 2.5 v, e n x = l ow operation 0 10 20 30 40 50 60 70 80 90 0 500 1000 1500 2000 current consumption per output (a) dat a r a te (kbps) v ddx output current 1 1845-008 0 2 4 0 20 40 figure 8. current consumpt ion per output vs. data rate for 2.5 v, en x = low operation 0 50 100 150 200 250 300 350 400 0 500 1000 1500 2000 current consumption per input ( a) d at a r a te (kbps) v ddx input current 1 1845-009 0 5 10 15 0 20 40 figure 9. current consumption per input vs. data rate for 3.3 v, en x = low operation 0 20 40 60 80 100 120 140 0 500 1000 1500 2000 current consumption per output (a) dat a r a te (kbps) v ddx output current 1 1845-010 0 2 4 0 20 40 figure 10 . current consumption per output vs. dat a rate for 3.3 v, en x = low operation 0 20 40 60 80 100 120 140 160 0 500 1000 1500 2000 current consumption per input (a) dat a r a te (kbps) v ddx input current 1 1845-0 1 1 0 0.5 1.0 0 5 10 figure 11 . current consumption per input vs. data rate for 2.5 v, en x = high operation 0 10 20 30 40 50 60 70 80 90 0 500 1000 1500 2000 current consumption per output (a) d at a r a te (kbps) v ddx output current 1 1845-012 0 0.5 1.0 0 5 10 figure 12 . current consumption per output vs. data rate for 2.5 v, e n x = high operation rev. 0 | page 15 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet 0 20 60 40 100 80 120 140 160 180 200 0 500 1000 1500 2000 current consumption per input (a) d at a r a te (kbps) v ddx input current 1 1845-013 0 0.5 1.0 0 5 10 figure 13 . current consumption per input vs. data rate for v ddx = 3.3 v, en x = high operation 0 20 40 60 80 100 120 140 0 500 1000 1500 2000 current consumption per output (a) dat a r a te (kbps) v ddx output current 1 1845-014 0 0.5 1.0 0 5 10 figure 14 . current consumption per output vs. data rate for v ddx = 3.3 v, en x = h igh operation 0 100 200 300 400 500 600 0 1 2 3 4 i ddx current (a) d at a input vo lt age (v) f alling rising 1 1845-015 figure 15 . typical i ddx current per input vs. data input v oltage for v dd x = 3.3 v 0 50 100 150 200 250 300 0 0.5 1.0 1.5 2.0 2.5 3.0 i ddx current (a) d at a input vo lt age (v) f alling rising 1 1845-016 figure 16 . i ddx current per input vs. data input v oltage for v dd x = 2.5 v 0 1 2 3 4 5 6 7 8 9 10 ?40 ?20 0 20 40 60 80 100 120 140 supp l y current/channe l (a) temper a ture (c) output input 1 1845- 1 17 figure 17 . typical input and output supply current per channel vs. temperature for v ddx = 2.5 v, data rate = 100 kbps 0 1 2 3 4 5 6 7 8 9 10 ?40 ?20 0 20 40 60 80 100 120 140 supp l y current/channe l (a) temper a ture (c) output input 1 1845- 1 18 figure 18 . typical input and output supply current per channel vs. temperature for v ddx = 3.3 v, data r ate = 100 kbps rev. 0 | page 16 of 24
data sheet adum1440/adum1441/adum144 2/adum1445/adum1446/adum1447 0 10 20 30 40 50 60 70 80 90 100 ?40 ?20 0 20 40 60 80 100 120 140 supp l y current/channe l ( a) temper a ture (c) output input 1 1845- 1 19 figure 19 . typical input and output supply current per channel vs. temperature for v ddx = 2.5 v, data rate = 1000 kbps 0 10 20 30 40 50 60 70 80 90 100 ?40 ?20 0 20 40 60 80 100 120 140 supp l y current/channe l (a) temper a ture (c) output input 1 1845-120 figure 20 . typical input and output supply current per channel v s. temperature for v ddx = 3.3 v, data rate = 1000 kbps 0 20 40 60 80 100 120 140 ?40 ?20 0 20 40 60 80 100 120 140 pro p ag a tion del a y (ns) temper a ture (c) v ddx = 2.5v v ddx = 3.3v 1 1845-121 figure 21 . typical propagation d elay vs. temperature for v ddx = 3.3 v or v dd x = 2.5 v 0 20 40 60 80 100 120 2.0 2.5 3.0 3.5 4.0 glitch fi l ter width (ns) transmitter v ddx (v) 1 1845-017 figure 22 . typical glitch filter operation threshold 0 20 40 60 80 100 120 140 ?40 ?20 0 20 40 60 80 100 120 140 refresh period (s) temper a ture (c) v ddx = 2.5v v ddx = 3.3v 1 1845-122 figure 23 . typical refresh period vs. temperature for 3.3 v and 2.5 v o peration 0 20 40 60 80 100 120 2.0 2.5 3.0 3.5 4.0 refresh period (s) v ddx vo lt age (v) 1 1845-123 figure 24 . typical refresh period vs. v ddx voltage rev. 0 | page 17 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet applications information p rinted circuit board (pcb) layout t he adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 digital isolator s require no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at both input and output supply pins : v dd1 a nd v dd2 ( see figure 25 ). choose a capacitor value between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm . using proper pcb de sign choices, t he adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 readily meet s cispr 22 class a (and fcc class a) emissions standards, as well as the more stringent cispr 22 class b (and fcc class b) standards in an unsh ielded environment. refer to the an - 1109 application note , recommendations fo r control of radiated emissions with icoupler devices , for pcb - related emi mitigation techniques, including board layout and stack - up issues. v dd1 gnd 1 v ia v ib v ic/ v oc v id/ v od en 1 gnd 1 v dd2 gnd 2 v oa v ob v oc/ v ic v od/ v id en 2 gnd 2 1 1845-018 f igure 25 . recommended printed circuit board layout for applications involving high common - mode transients, it is important to minimize board coupling across the isolation barrier. furthermore, design the board layout so that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch - up or permanent damage. propagation delay - related parameters th ese product s are optimized for minimum power consumpt io n by eliminating as many internal bias currents as possible. as a result, the timing characteristics are more sensitive to operating voltage and temperature than in standard i coupler products . r efer to figure 17 through figure 24 for the expected variation of these parameters. propagation delay is a parameter defined as the time it takes a logic signal to propagate through a component. the input - to - output propagation delay time for a high - to - low tr ansition can differ from the propagation delay time of a low - to - high transition. input (v ix ) output (v ox ) t plh t phl 50 % 50 % 1 1845-019 f igure 26 . propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and an indicati on of how accurately the timing of the input signal is preserved. channel - to - channel matching is the maximum amount of time the propagation delay differs between channels within a single adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 component. propagation d elay sk ew is the m aximum amount of time the propagation delay differs between multiple adum1440/ adum1441/adum1442/adum1445/adum1446/adum1447 compone nts o perating u nder t he same conditions . in edge - based systems, it is critical to reject pulses that are too short to be handled by the encode and decode circuits. the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 implement a glitch filter to reject pulses l ess than the glitch filter operating threshold. this threshold depends on the operating voltage , as shown in figure 22 . any pulse shorter than the glitch filter does not pass to the output. when the refresh circuit is enabled, pulses that match the glitch filter width have a small probability of being stretched until corrected by the next refresh cycle, or by the next valid data through that channel. to avoid issues with pulse stretching, observe the minimum pulse width requirement s listed in the switching specifications. dc correctness standard operating mode positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. the decoder is bistable and is, th erefore, either set or reset by the pulses, indicating input logic transitions. when refresh and watchdog functions are enabled by pull i ng en 1 and en 2 low, in the absence of logic transitions at the input for more than ~140 s, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than approximately 200 s, the input side is assumed unpowered or nonfunctional, in which case , the isolator watchdog circuit forces the output to a default state. the default state is either high as in the adum1440 , adum1441 , and adum1442 versions, or low as in the adum1445 , adum1446 , and adum1447 versions. low power operating mode the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 allow the refresh and watchdog functions to be disabled by pulling en 1 and en 2 to logic high for the lowest power consumption. these control pins must be set to the same value on each side of the component for proper operation. in this mode , the current consum p tion of the chip drops to the microamp range. however , be careful when using this mode because dc correctness is no longer guaranteed at startup . for example , if the follo wing sequence of events occurs : 1. p ower is applied to s ide 1 2. a high level is asserted on the v ia input 3. p ower is applied to s ide 2 rev. 0 page 18 of 24
data sheet adum1440/adum1441/adum144 2/adum1445/adum1446/adum1447 t he high on v ia is not automatically transferred to the s ide 2 v oa , and there can be a level mismatch that is not corrected unt il a tra n sit i on occurs at v ia . after power is stable on each side and a transition occurs on the input of the channel , that channel s input and output state is correctly matched. this contingency can be addressed in several ways, such as sending dummy data , or toggling refresh on for a short period to force synchronization after turn on. recommended input voltage for low power operation the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 implement s chmitt trigger input buf fers so that the devices operate cleanly in low data rate or noisy environments. schmit t triggers allow a small amount of shoot through current when their input voltage is not approximate to either v ddx or gnd x levels . this is because the two transistors a re both slightly on when input voltages are in the middle of the supply range. for many digital devices, this leakage is not a large p ortion of the total supply current and may not be noticed ; however, i n the ultralow power adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 , this leakage can be larger than the total operating current of the device and cannot be ignored. to achieve optimum power consumption with the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 , a lways drive the inputs as near to v ddx or gnd x levels as possible. figure 15 and figure 16 illustrate the shoot through leakage of an input ; therefore, whe reas the logic threshold s of the input are standard cmos levels, optimum power performance is achieved when the input logic levels are driven within 0.5 v of either v ddx or gnd x levels . magnetic field immun ity the magnetic field immunity of the adum1440 / adum1441 / adu m1442 / adum1445 / adum1446 / adum1447 is determined by the changing magnetic field, which induces a voltage in the receiving coil of the transformer large enough to either falsely set or reset the decoder. the following analysis defines the cond itions under which this can occur. the 3.3 v operating condition of the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 is examined because it represents the most typical mode of operation. the pulses at the transformer o utput have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/dt ) r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). r n is the radius of the n th turn in the receiving coil (cm). n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 and an imposed requirement that the induced voltage be, at most , 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. the result is s hown in figure 27. 1000 1 k 10 0 m 1 0 k m a x i m u m a ll o w ab l e m a g n e t i c fl u x ( k g a u ss ) 10 0 k 1 m 1 0 m magnetic field frequency (hz) 100 10 1 0.1 0.01 0.001 1 1845-020 figure 27 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.5 kgaus s induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurred during a transmitted pulse (and was of the worst - case polarity), it would re duce the received pulse from >1.0 v to 0.75 v, still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum1440 / adum1441 / adu m1442 / adum1445 / adum1446 / adum1447 transformers. figure 28 shows these allowable current magnitudes as a function of frequency for selected distances. as shown, the adum1440 / adum1441 / adum 1442 / adum1445 / adum1446 / adum1447 are extremely immune and can be affected only by extremely large currents operat ing at a high frequency very near to the component. for the 1 mhz example noted previously, a 1.2 ka current would have to be pl aced 5 mm away from the adum1440 / adum1441 / adum1442 / adum1445 / adu m1446 / adum1447 to affect the operation of the component. 1 k 10 0 m 1 0 k m a x i m u m a ll o w ab l e curr e n t ( ka ) 10 0 k 1 m 1 0 m magnetic field frequenc y (hz) distance = 5mm distance = 100mm distance = 1m 1000 100 10 1 0.1 0.01 1 1845-021 figure 28 . maximum allowable current for various current - to- adum144x spacings rev. 0 | page 19 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet note that at combinations of strong magnetic field and high frequency, any loops formed by pcb traces can induce error voltages sufficiently large enough to trigger th e thresholds of succeeding circuitry. take c are in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 isolat or is a function of the supply voltage, the data rate of the channel, and the output load of the channel. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi ( q ) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). f is the input logic signal frequency (mhz); it is half the input data rate, expressed in units of mbps. f r is the input stage refresh rate (mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). to calculate the total v dd1 and v dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 7 through figure 14 show per channel supply currents as a function of data rate for an unloaded output condition . insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing per formed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / adum1447 . analog devic es performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working v oltage. the values shown in table 17 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum csa approved working voltages. in many cases, the approved working v oltage is higher than the 50- year service life voltage. operation at these high working voltages can lead to shortened insulation life , in some cases. the insulation lifetime of the adum1440 / adum1441 / adum1442 / adum1445 / adum1446 / a dum1447 depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 29, figure 30 , and figure 31 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. the goal of a 50 - ye ar operating lifetime under the ac bipolar condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50 - year service life. the working voltages listed in table 17 can be applied while maintaining the 50- year minimum lifetime provided the voltage conforms to either the unipolar ac o r dc voltage case. treat a ny cross - insulation voltage waveform that does not conform to figure 30 or figure 31 as a bipolar ac waveform, and limit its peak voltage to the 5 0 - year lifetime voltage value listed in table 17 . note that the voltage presented in figure 30 is shown as sinusoidal for illustration purposes only. it is meant to represe nt any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 1 1845-022 figure 29 . bipolar ac waveform 0v rated peak voltage 1 1845-023 figure 30 . unipolar ac waveform 0v rated peak voltage 1 1845-024 figure 31 . dc waveform rev. 0 | page 20 of 24
data sheet adum1440/adum1441/adum144 2/adum1445/adum1446/adum1447 outline dimensions compliant t o jedec st andards mo-137-ab controlli ng dimensions are in inches; millimete r dimension s (in p arentheses ) are rounded-of f inch equiv alents for reference onl y and are not appropria te for use in design. 16 9 8 1 s e a t i n g p l a n e 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 4 ( 0 . 1 0 ) 0 . 0 1 2 ( 0 . 3 0 ) 0 . 0 0 8 ( 0 . 2 0 ) 0 . 0 2 5 ( 0 . 6 4 ) b s c 0 . 0 4 1 ( 1 . 0 4 ) r e f 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 6 ( 0 . 1 5 ) 0 . 0 5 0 ( 1 . 2 7 ) 0 . 0 1 6 ( 0 . 4 1 ) 0 . 0 2 0 ( 0 . 5 1 ) 0 . 0 1 0 ( 0 . 2 5 ) 8 0 coplanarity 0.004 (0.10) 0 . 0 6 5 ( 1 . 6 5 ) 0 . 0 4 9 ( 1 . 2 5 ) 0 . 0 6 9 ( 1 . 7 5 ) 0 . 0 5 3 ( 1 . 3 5 ) 0 . 1 9 7 ( 5 . 0 0 ) 0 . 1 9 3 ( 4 . 9 0 ) 0 . 1 8 9 ( 4 . 8 0 ) 0 . 1 5 8 ( 4 . 0 1 ) 0 . 1 5 4 ( 3 . 9 1 ) 0 . 1 5 0 ( 3 . 8 1 ) 0 . 2 4 4 ( 6 . 2 0 ) 0 . 2 3 6 ( 5 . 9 9 ) 0 . 2 2 8 ( 5 . 7 9 ) 01-28- 2008-a figure 32 . 16 - lead shrink small outline package [qsop] (rq - 16) (dimensions shown in inches and (millimeters) ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) default output state maximum propagation delay, 3.3 v (ns) temperature range package description package option adum1440arqz 4 0 2 high 180 ?40c to +125c 16- lead qsop r q -16 adum1441arqz 3 1 2 high 180 ?40c to +125c 16- lead qsop rq -16 ADUM1442ARQZ 2 2 2 high 180 ?40c to +125c 16- lead qsop rq -16 adum1445arqz 4 0 2 low 180 ?40c to +125c 16- lead qsop rq -16 adum1446arqz 3 1 2 low 180 ?40c to +125c 16- lead qsop rq -16 adum1447arqz 2 2 2 low 180 ?40c to +125c 16- lead qsop rq -16 1 z = rohs compliant part. 2 tape and reel is available. the addition of the C rl7 suffix indicates that the product is shipped on 7 tape and reel. rev. 0 | page 21 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet notes rev. 0 | page 22 of 24
data sheet adum1440/adum1441/adum144 2/adum1445/adum1446/adum1447 notes rev. 0 | page 23 of 24
adum1440/adum1441/adum1442/adum1445/adum1446/adum1447 data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their resp ective owners. d11845 - 0- 10/13(0) rev. 0 | page 24 of 24

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